Wide-fan-in OR Gates have large number of leaky parallel transistors connected between dynamic node and Ground and large dynamic node capacitance which increase delay. In this work, a new domino circuit called LECTOR Current Comparison Domino (LCCD) is proposed which has low power consumption and act as a potential drop switching device. The leakage current of LCCD is low in pull up network (PUN) and dynamic node capacitance is greatly reduced by using current mirror technique which can be used in dyanmic quasi adiabatic logics. The dynamic node is separated from the PUN using the current comparison stage and the loss in speed due to LECTOR configuration is compensated by increasing mirror ratio and allow the recycling of energy. LECTOR (LEakage Control TransisOR) is introduced in the path between pull-up network and the footer transistor reducing the static leakage current as well as dynamic switching current. LCCD is simulated using 16-nm high performance Predictive Technology Model (PTM) and 15% of power reduction was observed from LCCD for 64 bit OR gate compared with Current Comparison Domino (CCD).This dominos used in real time adiabatic circuits to realise battery operated applications-portable devices with high speed.