ISSN: 0973-7510

E-ISSN: 2581-690X

R. Varatharajan1 , Angeline Peace Preethi2 and K.G. Revathi3
1Department of ECE, Sri lakshmi Ammal Engineering College, Chennai, India.
2Anna University, Chennai, India.
3Department of ECE,DMI College of Engineering, Chennai, India.
J Pure Appl Microbiol. 2015;9(Spl. Edn. Aug.):71-77
© The Author(s). 2015
Received: 03/02/2015 | Accepted: 01/05/2015 | Published: 31/08/2015
Abstract

Physical layout automation is an important in VLSI’s field. With the advancement of semiconductor technology, VLSI is coming to VDSM (Very Deep Sub Micrometer), and the scale of the random logic IC circuits goes towards million gates. Physical design is the process of determining the physical location of active devices and interconnecting them inside the boundary of the VLSI chip the earliest and the most critical stage in VLSI layout design is the placement. The background is the rectangle packing problem: given a set of rectangular modules of arbitrary sizes, place them without overlap on a plane within a rectangle of minimum area. The VLSI placement problem is to place the object in the fixed area of die with out overlap and with some cost constrain. Such as the wire length and area of the die. The wire length and the area optimization is the major task in the physical design. We first introduced about the major technique involved in the algorithm.

Keywords

Placement problems, Memetic algorithm, Wire length minimization, Area minimization

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